The DDR5 specification is released, unveiling the next generation of memory wars!
On July 15, JEDEC officially announced the new DDR5 standard, which is the next generation of high-performance computing systems. According to JEDEC, DDR5 is designed to meet a variety of high-efficiency and high-performance requirements, including not only client systems, but also high-performance servers, providing a new memory technology for future data center and computer reforms.
According to IDC research data, the demand for DDR5 will gradually increase from 2020, and will occupy 22% of the DRAM market in 2021, and its market share will reach 43% in 2022.
Theoretical DRAM bandwidth vs number of cores / Micron
In the era of rapid development of computing power, CPU manufacturers are still increasing the number of cores. In the past, PC users used quad-core CPUs. Now most CPU manufacturers have provided six-core or even twelve-core high-end chips in the consumer market. In server applications, the number of CPU cores has been as high as 64 cores. Server memory solutions such as DDR4 have begun to struggle to meet the bandwidth requirements of multi-core CPUs.
Signal integrity, power output, and layout complexity all limit the bandwidth on each CPU core. Therefore, a new memory architecture is needed to give play to the true performance of the next-generation CPU, which is also one of the original intentions of DDR5.
DDR4 and DDR5 bandwidth comparison / Micron
DDR5 can achieve higher data transfer rates, lower power consumption and higher density. In terms of data transfer rate, the maximum transfer rate of DDR5 can reach 6400 MT/s, which is twice that of DDR4. SK Hynix has also begun to develop 8400MT/s DDR5 memory. Compared with DDR4-3200, DDR5-6400 can achieve more than twice the bandwidth.
Comparison of several generations of DDR memory
In order to increase the transfer rate of the memory, DDR5 has several new features:
1. Multi-tap Decision Feedback Equalizer (DFE): By opening the data eye diagram in the device, DFE reduces inter-symbol interference (ISI) at high rates
2. Duty cycle adjustment (DCA) circuit: This circuit can adjust the DQ and DQS duty cycle for the internal read path. When these signals are transmitted in the equipment and PCB, this function can correct the naturally occurring small duty cycle distortion, and finally optimize the duty cycle of the DQ and DQS signals received by the controller.
3. DQS intermittent oscillator circuit: This circuit allows the controller to monitor the delay caused on the DQS clock tree due to voltage and temperature drift. In this case, the controller design can actively decide whether or when to retrain, thereby optimizing the timing of writing.
4. Reading training mode with independent mode register: Related data modes include the default programmable serial mode, a simple four modes, and a mode generated by a linear feedback shift register, which provides more for high data transfer rate Ample time gap.
5. Internal reference voltage: control and address pin and chip select pin reference voltage. The internal reference voltage of the DQ pin improves the voltage margin on the DQ receiver, and the internal reference voltage of these pins improves the voltage margin on the corresponding receiver respectively, allowing the device to achieve a higher data transmission rate .
JEDEC predicts that the overall promotion curve of DDR5 is similar to the previous DDR standards, so we may not see DDR5 memory appear in the equipment until 12 to 18 months. But as the technology industry matures, JEDEC also predicts that the shelf life of DDR5 will be longer than that of DDR4. According to the current development rate of major manufacturers, we will see their DDR5 samples and commercial DIMMs in the next period of time. We believe that next year's server market and client desktop market will usher in new changes.
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